In many high performance, high density semiconductor devices, Cu or Cu alloy is used for the conductive material in the metallization layers. Cu or Cu alloy is generally preferred over aluminum-based metallization in these applications because Cu is a better electrical conductor and is more resistant than aluminum to electromigration. Cu interconnect structures found in these semiconductor devices comprise a substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed low-k interlayer dielectrics and patterned conductive structures formed from Cu (or Cu alloy) based metallization.
But, because Cu diffuses through the low-k interlayer dielectric materials, the Cu interconnect structures must be encapsulated by a diffusion barrier layer. Otherwise the diffused Cu metal in the low-k interlayer dielectric will result in current leakage between the interconnect structures. The diffusion barrier is typically a metal layer. Typical metal diffusion barrier metals include tantalum, tantalum nitride, titanium, titanium nitride, titanium-tungsten, tungsten, tungsten nitride, titanium silicon nitride, tungsten silicon nitride, tantalum silicon nitride and silicon nitride.
Shown in FIG. 1 is a schematic cross-sectional diagram of a Cu interconnect structure 150 having a conventional diffusion barrier, a Cu capping layer 130. A Cu interconnect structure 150 and a low-k interlayer dielectric layer 110 are formed on a substrate 100. The substrate 100 may be any surface, generated when making a semiconductor device, upon which a dielectric layer may be formed. The bottom and sides of the Cu interconnect structure 150 are encapsulated with a barrier layer 120 to prevent Cu from diffusing into the low-k interlayer dielectric 110. The barrier layer 120 typically comprises a blanket layer of refractory material, such as, tantalum, tantalum nitride, or titanium nitride. The exposed top surface of the Cu interconnect structure 150 is then capped with a diffusion barrier layer 130 of thin silicon nitride barrier. Generally, another dielectric layer or other type of passivation layer 140 may be deposited on top of the structure shown in FIG. 1 and the Cu capping layer 130 prevents Cu from diffusing into the surrounding low-k interlayer dielectric 110, which could result in electrical short between the Cu interconnect structure 150 and another neighboring Cu interconnect structure 151. The neighboring Cu interconnect structure 151 is encapsulated with its own set of diffusion barriers 121 and 131. The capping diffusion barriers 130 and 131 prevent copper diffusion between the metal lines 150 and 151 which would cause unwanted electrical shorts.
The Cu capping process involves depositing a blanket of a diffusion barrier material, silicon nitride, and then removing the excess material from the top surface of the surrounding interlayer dielectric 110 by chemical-mechanical polishing (CMP). After removing the excess barrier material by CMP, the Cu capping layer 130 remains over the Cu interconnect structure 150. This conventional method of capping the Cu in damascene process is generally complex and costly and economical alternate process solutions are helpful in reducing the manufacturing costs.